1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and imaging apparatus, which compare a pixel signal and a reference signal that varies in a stepwise manner and obtains a digital value from an amount of time for the change of the levels of their voltage.
2. Description of the Related Art
Presently, a solid-state imaging apparatus such as a CCD (Charge Coupled Device) and a CMOS (Complementary Metal Oxide Semiconductor) has been used for various applications. Recently, a MOS (Metal Oxide Semiconductor) type solid-state imaging apparatus suitable for faster imaging has received attention, and various architectures have been proposed.
JP-A-2005-278135 (Patent Document 1) achieves a higher frame rate by using an up/down counter, without increasing the size of the circuit. FIG. 13 is a block diagram showing an embodiment of the MOS type solid-state imaging apparatus that employs the method.
That is, a solid-state imaging apparatus 1 includes a pixel array section 10, a row scanning circuit 13 and a column scanning circuit 14, a reference signal generating section (DAC) 15, a comparator 16, an up/down counter (U/D CN) 17, a buffer (BUF) 18, and a drive control section 21. In the pixel array section 10, unit pixels 12 are placed in a matrix form. The row scanning circuit 13 and column scanning circuit 14 drive the pixel array section 10. The reference signal generating section (DAC) 15 generates a reference voltage. The comparator 16 compares a vertical signal line voltage and a reference voltage. The up/down counter (U/D CN) 17 performs both digital operation and storage. The buffer (BUF) 18 temporarily retains the values. The drive control section 21 controls all of those components.
The reference signal generating section 15 and the comparator 16 and up/down counter 17 at each column are included in an A/D converting circuit Ramp DAC in the scheme and converts an analog signal obtained from a pixel to a digital value. The A/D converting circuit compares a pixel signal and a reference signal the value of which varies in a stepwise manner in the comparator and obtains the digital value by counting the amount of time for changing the levels of their voltages.
Many MOS type imaging apparatus obtain a vertical signal line voltage level upon reset of a pixel, then obtain the voltage level of the vertical signal line when light is input, and obtain the difference between them to perform an operation of removing fixed pattern noise.
In the solid-state imaging apparatus 1 case, the up/down counter 17 is used to remove the fixed pattern. First, in order to perform D/A conversion at the reset level of a pixel, the counter counts minus levels. Next, in order to perform D/A conversion upon input of light, the counter counts plus levels from the counts as the starting point. Thus, the difference can be obtained in the digital area, without any subtractor circuit (refer to FIG. 14).
The reference signal generating section, which generates a reference signal, is connected commonly to the comparators at all columns, and the counter is provided independently at each column. The digital data from which a fixed pattern has been removed is stored in the buffer 18 once and is sequentially transferred from the end column.
The comparator 16 employed in the solid-state imaging apparatus 1 may be a switched capacitor. FIG. 15 shows the circuit example. A switch transistor Tr 21 is connected between the gate and drain of a transistor Tr23. A switch transistor Tr 22 is connected between the gate and drain of a transistor Tr 24.
A pixel signal is input to the transistor Tr 23 through a capacitor Cp 25, and a signal waveform from the reference signal generating section is input to the transistor Tr 24 through a capacitor Cp 26. The comparator is a circuit that generates a High or Low output L27 according to the height of the voltage levels of the signals on the pixel signal side and the RAMP side.
It is important for the circuit to determine the criterion-of-judgment voltage for the comparison first. The operation of determining the voltage will be called “auto-zero” hereinafter. In order to perform the auto-zero, a vertical signal line reset level is input to the pixel signal side while a ramp reference signal is input to the reference signal generating section side.
A PSET signal for performing the auto-zero is commonly supplied to the gates of the switch transistors Tr 21 and Tr 22. FIG. 16 shows the timing of the PSET signal. The Tr 21 and Tr22 are turned on at the time when the PSET signal falls, and the comparator enters the auto-zero state. The operation point is determined when the gate voltages of the Tr 23 and Tr 24 are equal, and the circuit reaches equilibrium.
Then, the Tr 21 and Tr 22 are turned off at the time when the PSET signal rises, and both of the gates of the Tr 23 and Tr 24 float. Here, the difference between the voltage of the vertical signal line and the gate voltage of the Tr 23 is retained in the capacitor Cp 25, and the difference between the RAMP reference voltage and the gate voltage of the Tr 24 is retained in the capacitor Cp 26. After the auto-zero, the levels of the pixel signal and the RAMP side signal can be compared.
However, the comparator has problems as follows:
(1) First Problem
At the rising edge of the auto-zero pulse PSET signal, the switch transistors Tr 21 and Tr 22 are turned off. At the same time, feedthrough occurs between the gate and drain of each of the switch transistors. Due to the influence by the feedthrough, a difference occurs between the gate potentials of the Tr 23 and Tr 24. This is caused by the unequal loads across the comparator. The lateral asymmetry of the loads connecting to the comparator may be a cause of the difference due to the facts that the comparator output signal line is connected to the drain side of the Tr 22 and/or that the load of the RAMP signal line connecting to the Cp 26 is light while the load of the VSL connecting to the Cp 25 is significantly heavy, for example. The magnitude of the feedthrough strongly depends on the rising time of the PSET signal. An abrupt PSET signal rise increases the feedthrough more and causes a large difference between the gate voltage of the Tr 23 and the gate voltage of the Tr 24. In this circuit example, it is known that the gate voltage of the Tr 23 decreases more than the gate voltage of the Tr 24 when feedthrough occurs after the auto-zero. If no feedthrough occurs, the gate voltage level of the Tr 23 positions substantially at the middle of that of the reset level detection ramp wave. Therefore, the counter counts about half (refer to the curve A in FIG. 16). However, if the gate potential of the Tr 23 is decreased by the feedthrough, the reset counts increases since the point of intersection with the reset detection ramp wave moves backward correspondingly (refer to the curve B in FIG. 16). If a large feedthrough occurs, the gate potential of the Tr 23 does not intersect with the reset level detection ramp wave (refer to the curve C in FIG. 16). In this case, the reset counter stops at the full code. However, the actual intersection has not been achieved, and the difference therefore becomes an error, which may deteriorate the image quality.
(2) Second Problem
FIG. 17 is a diagram showing the layout of the comparators at columns and the PSET signal generating circuit in the solid-state imaging apparatus. In the comparator 16 at a column near the reset signal generating section 19, a larger feedthrough occurs during the auto-zero. As the distance from the reset signal generating section 19 increases, the wiring resistance on the signal transmission path increases and the degree of dullness of the PSET pulses to be transmitted to the columns increases, which therefore decreases the amount of feedthrough to the columns. An abrupt rise of a PSET signal may increase the degree of dullness due to the signal transmission. Therefore, the reset counts largely differ among columns from end to end the ends of a column. In order to perform reset counting without an error at all columns against the factor and other variation factors, it is important for the sensor to take a longer reset count period (refer to FIG. 18).